A thin film transistor liquid crystal display (TFT-LCD) has been paid more and more attention over the years. At present, a high-resolution low-power TFT-LCD has become a focus of research and development.
The high-resolution low-power TFT-LCD needs to form a non-photosensitive resin structure of low dielectric constant. FIG. 1 shows a cross-sectional diagram of an array substrate provided with the non-photosensitive resin structure. As shown in FIG. 1, the array substrate is divided into a pixel region and a region of gate on array (region of GOA), respectively positioned on a left side and a right side of a dotted line in the diagram, and these two regions are formed simultaneously by a plurality of patterning processes. The array substrate comprises: a gate electrode 102 and a gate line (not shown) formed in a display region of a substrate 101, and a gate lead 102′ in the region of GOA; a gate insulating layer 103 covering the entire substrate 101 and formed above the gate electrode 102 and the gate line (not shown); an active layer 104 formed above the gate insulating layer 103; an ohmic contact layer 105 formed above the active layer 104; a source/drain electrode 107 formed on the ohmic contact layer 105 and the gate insulating layer 103, and a metal layer 107′ disposed in the same plane as the source/drain electrode 107 and formed simultaneously with the source/drain electrode 107 in the region of GOA, the metal layer being connected to the gate lead through a via hole 115 in the gate insulating layer 103; a planarization layer 109 formed above the source/drain electrode 107 and the metal layer 107′ and on the gate insulating layer 103; a pixel electrode 110 formed on the planarization layer 109 and connected to the source/drain electrode 7 through a via hole 116 in the planarization layer 109; a first passivation layer 111 formed on the planarization layer 109 and the pixel electrode 110; a common electrode 112 formed on the first passivation layer 111, and an electrode 117 disposed in the same layer as the common electrode 112, connected to the metal layer 107′ disposed in the same layer as the source/drain electrode 107 through the via hole 115 passing through the first passivation layer 111 and the planarization layer 109 in the region of GOA.
Currently, since a planarization layer is manufactured, a large number of masks are required, and generally, manufacturing the structure as shown in FIG. 1 requires eight patterning processes, which are: a first patterning process for forming the gate electrode 102, the gate line (not shown) and the gate lead 102′; a second patterning process for forming the gate insulating layer 103; a third patterning process for forming the active layer 104 and the ohmic contact layer 105; a fourth patterning process forming the source/drain electrode 107 and the metal layer 107′ disposed in the same layer as the source/drain electrode 107; a fifth patterning process for forming the planarization layer 109; a sixth patterning process for forming the pixel electrode 110; a seventh patterning process for forming the first passivation layer 111; and an eighth patterning process for forming the common electrode 112 and an electrode 112′ disposed in the same layer as the common electrode 112. Therefore, a large number of masks are needed, such that the manufacturing process is complex, and productivity is relatively low.